Verilog module "«font style◊bold»«field◊module»«font style◊plain»" is a Linear Feedback Shift Register (LFSR) used as an interval counter. The counter reaches terminal count after «field◊count» «get◊edge» clocks. «if true◊«button◊tc enable»◊'«field ◊terminal count»' is asserted «if true◊«button◊tc polarity»◊high◊else◊low» at the end of count for one cycle.» The count is preset synchronously on the «get◊edge» of the clock by an active «if true◊«button◊preset polarity»◊high◊else◊low» on '«field◊preset»'.«if true◊«button◊retriggerable»◊ The counter is free running, it presets itself on every terminal count.◊else◊ The counter is one shot, itstops counting after terminal count and must be preset to count again.» «if true◊«button◊ce enable»◊ The counting is suspended when '«field◊clock enable»' is asserted «if true◊«button◊ce polarity»◊high◊else◊low».»«if true◊«button◊sr enable»◊ The shift register output of the counter is brought out of the module as '«field◊shift register output»'.»«if true◊«button◊combinatorial»◊ The counter uses AND (or NAND) gates on the output of the shift register to detect for terminal count of all 'ones'.◊else◊ The counter uses small auxiliary counter to detect for terminal count by counting all 'ones' being shifted into the main counter. The preset of the small auxiliary counter is connected to the input of the main shift register and terminal count is generated only when «get◊stages» '1' bits have shifted into the main counter.The auxiliary counter has «get◊auxiliary stages» registers with two taps feedback to the input.» The main counter has «get◊stages» registers with «get◊tap count» taps of feedback to the input.
